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Design of a Miller amplifier using gm/ID based on a first-order building block approximation

In this paper the gm/ID methodology for designing analog CMOS circuits is used. As a case of study the single-ended Miller OTA design is widely discussed and analized. In order to show the advantage of gm/ID it is demonstrated that the first order building block approximation allows to understand not only how to correctly do the sizing of each transistor, but also the physical meaning of each small signal design model. This design flow is carried out by using design rules of a 130 nm CMOS technology, where Cadence is used for performing simulations at transistor level, obtaining results that confirm the usefullnes of the design models and the basics' veracity.